The present invention relates to field-effect transistors, in particular double-diffused metal-oxide-semiconductor (xe2x80x9cDMOSxe2x80x9d) transistors, and their method of manufacture.
A DMOS transistor is a type of field-effect transistor (xe2x80x9cFETxe2x80x9d) that can be used as a power transistor, that is, a transistor that is used to switch or control relatively large amounts of electrical power compared to a transistor that might be used in a logic circuit application. Power transistors might operate between 1-1000 volts, or higher, and might carry from several tenths of an amp to several amps of current, or higher. Power MOSFETs are designed to operate under conditions that would destroy conventional MOSFETs, or accelerate their failure.
Design of DMOS transistors presents challenges over other conventional MOS transistor devices, in particular relating to the structure of the channel and drain regions. FIGS. 1 and 2 illustrate a conventional trench DMOS transistor 100 and planar DMOS transistor 200, respectively. FIG. 1 shows a semiconductor substrate 102 with a trench 110 formed to a predetermined depth into the substrate. At the bottom of the substrate is an n+ drain region 120. Above the drain is an epitaxial layer 125 doped to a lighter degree of the same conductivity as the drain region. Overlying the epitaxial region is a channel region 105 implanted with a dopant having a polarity that is opposite the substrate and epitaxial regions. As illustrated in FIG. 1, the dopant profile ranges from a lesser degree to a greater degree away from the trench, to where a concentration of dopant forms a body region.
Formed near the surface of the substrate on either side of the trench are source regions 130, implanted with a dopant of the same conductivity type as the drain. Source and drain regions of the transistor shown in FIG. 1 are illustrated as n+, the channel region as pxe2x88x92, and a body region as p+. It should be readily apparent to a person skilled in the art that the polarity of the conductivity type for the transistor structure could be reversed. A dielectric layer 112 lines the trench. Filling the trench over the dielectric layer is a gate 114, which is typically made of polysilicon material doped to a similar conductivity type as the source and drain regions.
In operation, a charge applied to the gate creates a channel for electron migration across a channel 132 alongside the trench between the sources 130 and the epitaxial region 125, and flowing to the drain 120. The charge applied to the gate also forms an accumulation area 134 in the epitaxial layer under the trench, where electrons accumulate.
FIG. 2 illustrates a conventional planar DMOS transistor 200 fabricated on a semiconductor substrate 202. An n+ drain region lies at the bottom of the substrate. Overlying the drain is an nxe2x88x92 epitaxial layer 225. Source regions 230 are formed of an implant of n+ dopants into an area just below the top surface of the substrate. Surrounding each source region underneath are P-type channel regions 205, which form a channel 232 between the source and the epitaxial layer. At least partially overlying each source region is a dielectric layer 212. Coextensively overlying the dielectric layer is a polysilicon gate 214 implanted with dopants of the same conductivity type as the source regions.
A charge applied to the gate causes electrons to flow from the sources, across the channels to the epitaxial region, and then down to the drain. Because of the uniform charge on the gate, an accumulation of electrons forms at the surface in the epitaxial layer just below the gate, between the channel regions, in an accumulation area 234.
An important design issue for both trench and planar DMOS transistors is the gate charge required to drive the gate of the MOSFET to a specific voltage. FIG. 3 illustrates an ideal gate charge curve for a conventional DMOS transistor. In a particular range, denoted as the Miller Q range, additional charge on the gate is insufficient to overcome certain parasitic capacitance that arise during operation. Several important ones of the parasitic capacitance are labeled in FIGS. 1 and 2. A capacitance between the gate and the source, Cgs, forms in the area where the gate overlaps the source. A gate-to-drain capacitance, Cgd, forms between the gate and the accumulation region, where electrons accumulate as a current path is formed from the channel region to the drain.
The capacitance Cgd is also known as the xe2x80x9cMiller capacitance.xe2x80x9d The Miller capacitance is an effective build-up of capacitative charge which must be overcome in order to bias the transistor to a particular voltage, as shown in FIG. 3. Increasing the gate charge has adverse effects. Transistor switching speed is significantly reduced where a larger gate charge is required. Further, the failure rate of transistors subject to higher gate charge is increased. Thus, it is desired to minimize the Miller capacitance over a range of charge, so as to reduce the gate charge and enhance transistor switching speed, efficiency, and improve failure rates.
One method of reducing the Miller capacitance is shown in U.S. Pat. No. 5,879,994, which describes a process and structure to apply a non-uniform gate dielectric layer, where a thicker oxide is applied over the accumulation area, and a thinner oxide is formed over the inversion channel area. The extra-thick oxide, or xe2x80x9cterrace oxidexe2x80x9d over the region where the Miller capacitance occurs, has some limitations. First, for planar DMOS transistors, alignment of the terrace oxide is difficult to achieve, and adds significantly to the costs of manufacturing the devices. Being easily misaligned, transistors formed with a terrace oxide have substantially lower yields. The difficulty with which to build a nonuniform dielectric layer exists in trench DMOS structures as well.
An alternative approach for reducing the Miller capacitance begins by considering voltage-dependent capacitance characteristics of MOS devices under various gate bias conditions. FIG. 4 shows a well-known CV curve for a conventional MOS device. At the extremes of the applied gate voltage |Vg|, the capacitance value maintains a constant value that depends only on the thickness of the dielectric (assumed to be SiO2, although not limited herein as such). This is due to a layer of mobile charge, at the extreme points on the curve, which causes the interface between the dielectric and the silicon substrate to effectively become a second plate of a capacitor.
As the gate voltage approaches a value known as the xe2x80x9cflat bandxe2x80x9d voltage, as viewed from the accumulation side, the capacitance begins to decrease until a point called the xe2x80x9cthresholdxe2x80x9d voltage is reached. This point is reached when the mobile charge distribution near the SiO2xe2x80x94Si interface transitions from accumulation to inversion. Beyond the threshold voltage Vt, the area immediately around the SiO2xe2x80x94Si interface is said to be inverted and there is again a layer of mobile charge, albeit of opposite polarity. In this range the MOS capacitance is limited by the gate oxide thickness.
Close to the threshold Vt, there is a point Cmin that represents the lowest value of capacitance for a given gate bias voltage in conventional MOS devices. However, a novel DMOS structure could be made so as to shift Cmin to as near the Vgs value range for the Miller region shown in FIG. 3. This would lower the capacitance within the Miller range, and effectively decrease the range of charge needed to overcome the Miller capacitance.
The present invention provides a method of fabricating a gate structure of a DMOS device. The fabrication method includes the steps of forming a polysilicon gate on a portion of a semiconductor substrate, implanting a dopant of a first conductivity type into the polysilicon gate, masking the polysilicon gate to define an alternation region within the gate, and implanting a dopant of a second conductivity type into the alternation region, where the second conductivity type has an electrical polarity opposite a polarity of the first conductivity type.
In another embodiment, the present invention provides a gate of a semiconductor device that includes a polysilicon gate structure overlying a channel region in a semiconductor substrate and extending at least partially over a source formed in the substrate adjacent the channel region. The polysilicon gate structure has a first portion being of a first conductivity type and a second portion being of a second conductivity type defining an alternation region. The second conductivity type has a polarity that is opposite a polarity of the first conductivity type.
In yet another embodiment, the present invention provides a method of fabricating a gate structure of a trench-type DMOS device. The method includes the steps of forming a trench in a semiconductor substrate, lining the trench with a dielectric layer, and forming a first polysilicon gate portion to an intermediate depth of the trench. The method further includes the steps of implanting a dopant of a first conductivity type into the first gate portion, forming a second polysilicon gate portion in the trench over the first gate structure to a level substantially equal to a top surface of the silicon substrate, and implanting a dopant of a second conductivity type into the second gate portion.
In still yet another embodiment, the present invention provides a composite gate structure in a trench transistor. The composite gate structure includes a trench extending a selected depth from a top surface of a semiconductor substrate, a conformal dielectric layer lining the trench, a first gate portion disposed over the dielectric layer and extending from the bottom to an intermediate depth of the trench, the first gate portion having a first conductivity type, and a second gate portion disposed over the first gate portion and the dielectric layer, and extending from the intermediate depth to the top surface, the second gate portion having a second conductivity type that is of an opposite polarity from the first conductivity type.
In still yet another embodiment, the present invention provides a semiconductor device having a channel region of a first conductivity type formed by diffusing a dopant of the first conductivity type into a substrate having a second conductivity type, a gate dielectric disposed on the substrate, and an implant region of a second conductivity type formed by diffusing a dopant of the second conductivity type under the gate dielectric, the second conductivity type having a polarity opposite a polarity of the first conductivity type.